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style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0!important;text-align:left;visibility:hidden;width:0"></th></tr></table></th> </tr></tbody></table><table class="row sub-header"style="background:#00837E;border-collapse:collapse;border-spacing:0;display:table;padding:0;position:relative;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><th class="small-12 large-12 columns first last" style="Margin:0 auto;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0 auto;padding:0;padding-bottom:16px;padding-left:30px;padding-right:30px;text-align:left;width:570px"><table style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tr style="padding:0;text-align:left;vertical-align:top"><th style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0;text-align:left"><table class="spacer" style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><td height="16px" style="-moz-hyphens:auto;-webkit-hyphens:auto;Margin:0;border-collapse:collapse!important;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;hyphens:auto;line-height:16px;margin:0;mso-line-height-rule:exactly;padding:0;text-align:left;vertical-align:top;word-wrap:break-word"> </td></tr></tbody></table> <h4 class="text-center" style="-moz-hyphens:none;-webkit-hyphens:none;Margin:0;Margin-bottom:10px;color:#fff;font-family:Montserrat,Arial,sans-serif;font-size:18px;font-weight:400;hyphens:none;line-height:22px;margin:0;margin-bottom:10px;padding:0;text-align:center;text-transform:uppercase;word-break:none;word-wrap:normal">News From Inspur Electronic Information Industry Co., Ltd</h4><h5 class="text-center" style="-moz-hyphens:none;-webkit-hyphens:none;Margin:0;Margin-bottom:10px;color:#fff;font-family:Montserrat,Arial,sans-serif;font-size:14px;font-weight:500;hyphens:none;line-height:18px;margin:0;margin-bottom:0;padding:0;text-align:center;word-break:none;word-wrap:normal">Transmitted by PR Newswire for Journalists on <span class="prevent-break" style="display:inline-block">August 24, 2018 06:20 PM EST </span></h5></th><th class="expander" style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0!important;text-align:left;visibility:hidden;width:0"></th></tr></table></th></tr></tbody></table><table class="row header" style="background:#e5f2f3;border-collapse:collapse;border-spacing:0;display:table;padding:0;position:relative;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><th class="small-12 large-12 columns first last" style="Margin:0 auto;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0 auto;padding:0;padding-bottom:0;padding-left:30px;padding-right:30px;text-align:left;width:570px"><table style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tr style="padding:0;text-align:left;vertical-align:top"><th style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0;text-align:left"> <table class="spacer" style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><td height="24px" style="-moz-hyphens:auto;-webkit-hyphens:auto;Margin:0;border-collapse:collapse!important;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:24px;font-weight:400;hyphens:auto;line-height:24px;margin:0;mso-line-height-rule:exactly;padding:0;text-align:left;vertical-align:top;word-wrap:break-word"> </td></tr></tbody></table> <h1 style="Margin:0;Margin-bottom:10px;color:#4D4E53;font-family:Montserrat,Arial,sans-serif;font-size:20px;font-weight:500;line-height:28px;margin:0;margin-bottom:0;padding:0;text-align:left;word-wrap:normal">Inspur Releases TensorFlow-Supported FPGA Compute Acceleration Engine TF2</h1> <table class="spacer" style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><td height="24px" style="-moz-hyphens:auto;-webkit-hyphens:auto;Margin:0;border-collapse:collapse!important;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:24px;font-weight:400;hyphens:auto;line-height:24px;margin:0;mso-line-height-rule:exactly;padding:0;text-align:left;vertical-align:top;word-wrap:break-word"> </td></tr></tbody></table> </th><th class="expander" style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0!important;text-align:left;visibility:hidden;width:0"></th></tr></table></th> </tr></tbody></table> <table class="row content" style="background:#fff;border-collapse:collapse;border-spacing:0;display:table;padding:0;position:relative;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><th class="small-12 large-12 columns first last" style="Margin:0 auto;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0 auto;padding:0;padding-bottom:16px;padding-left:30px;padding-right:30px;text-align:left;width:570px"><table style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tr style="padding:0;text-align:left;vertical-align:top"><th style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0;text-align:left"> <table class="spacer" style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><td height="24px" style="-moz-hyphens:auto;-webkit-hyphens:auto;Margin:0;border-collapse:collapse!important;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:24px;font-weight:400;hyphens:auto;line-height:24px;margin:0;mso-line-height-rule:exactly;padding:0;text-align:left;vertical-align:top;word-wrap:break-word"> </td></tr></tbody></table><p><span class="xn-location">FREMONT, Calif.</span>, <span class="xn-chron">Aug. 24, 2018</span> /PRNewswire/ -- On <span class="xn-chron">August 23</span>, at KDD2018 <span class="xn-location">London</span> -- a premier global conference focused on artificial intelligence -- Inspur released the FPGA computing acceleration engine TF2 supporting TensorFlow, which helps AI customers quickly implement FPGAs based on mainstream AI training software and deep neural network model DNN on inference. It delivers high performance and low latency for AI applications through the world's first DNN shifting technology on FPGAs.</p>
<p>At present, using the FPGA technology to achieve customizable, low latency, high performance and high power-consumption ratio for AI inference application has become the technical route adopted by many AI companies. However, before FPGA technology enters into large-scale AI business deployment, there are still many challenges such as high software writing threshold, limited performance optimization, and difficult power control. The goal of Inspur's TF2 Compute Acceleration Engine is to solve these challenges for customers. </p>
<p>The TF2 computing acceleration engine consists of two parts. The first part is the model optimization conversion tool TF2 Transform Kit, which optimizes and transforms the deep neural network model data trained by the framework such as TensorFlow. It greatly reduces the size of the model data file, as it can compress 32-bit floating-point model data into a 4-bit integer data model, making the actual model data file size smaller than the original 1/8 and basically keeps the rule storage of the original model data. The second part is the FPGA intelligent running engine TF2 Runtime Engine. It can automatically convert the previously optimized model file into FPGA target running file. In order to eliminate the dependence of deep neural network such as CNN on FPGA floating-point computing power, Inspur designed the innovative shift computing technology, which can quantize 32-bit float-point into 8-bit integer data. Combined with the aforementioned 4-bit integer model data, the conversion convolution operation floating-point multiplication is calculated as an 8-bit integer shift operation, which greatly improves the FPGA for inference calculation performance and effectively reduces its actual operating power consumption. This is also the world's first case of implementing the shift operation of deep neural network DNN on FPGA under the premise of maintaining the accuracy of the original model.</p>
<p>The SqueezeNet model on the Inspur F10A FPGA card shows excellent computational performance for the TF2 computing acceleration engine. The F10A is the world's first half-height and half-length FPGA accelerator card to support the Arria 10 chip. SqueezeNet is a typical convolutional neural network architecture which is a streamlining model but its accuracy is comparable to AlexNet. It is especially suitable for image-based AI applications with high real-time requirements. Running the SqueezeNet model optimized by the TF2 engine on the F10A, the calculation time of a single picture is 0.674ms while maintaining the original accuracy. It is slightly better than the currently widely used GPU P4 accelerator card in terms of calculation accuracy and delay. </p>
<div>
<table border="1" cellpadding="0" cellspacing="0" class="prntblns">
<tbody>
<tr>
<td class="prnsbts prnrbrs prnvab prnsbbs prntac prnpl6 prnsbls prnpr6"> <p class="prnews_p"><span class="prnews_span">Device</span></p> </td>
<td class="prngen3"> <p class="prnews_p"><span class="prnews_span">Peak Power</span></p> </td>
<td class="prngen3"> <p class="prnews_p"><span class="prnews_span">Date Type</span></p> </td>
<td class="prngen3"> <p class="prnews_p"><span class="prnews_span">Top1</span></p> </td>
<td class="prngen3"> <p class="prnews_p"><span class="prnews_span">Top5</span></p> </td>
<td class="prngen3"> <p class="prnews_p"><span class="prnews_span">FPS (images/s)</span></p> </td>
</tr>
<tr>
<td class="prngen4"> <p class="prnews_p"><span class="prnews_span">F10A </span></p> </td>
<td class="prngen5"> <p class="prnews_p"><span class="prnews_span">45W</span></p> </td>
<td class="prngen5"> <p class="prnews_p"><span class="prnews_span">INT8</span></p> </td>
<td class="prngen5"> <p class="prnews_p"><span class="prnews_span">57.62%</span></p> </td>
<td class="prngen5"> <p class="prnews_p"><span class="prnews_span">79.98%</span></p> </td>
<td class="prngen6"> <p class="prnews_p"><span class="prnews_span">1484</span></p> </td>
</tr>
<tr>
<td class="prngen4"> <p class="prnews_p"><span class="prnews_span">P4</span></p> </td>
<td class="prngen5"> <p class="prnews_p"><span class="prnews_span">75W</span></p> </td>
<td class="prngen5"> <p class="prnews_p"><span class="prnews_span">FP32</span></p> </td>
<td class="prngen5"> <p class="prnews_p"><span class="prnews_span">58.14%</span></p> </td>
<td class="prngen5"> <p class="prnews_p"><span class="prnews_span">80.79%</span></p> </td>
<td class="prngen6"> <p class="prnews_p"><span class="prnews_span">1323</span></p> </td>
</tr>
<tr>
<td class="prngen4"> <p class="prnews_p"><span class="prnews_span">P4</span></p> </td>
<td class="prngen5"> <p class="prnews_p"><span class="prnews_span">75W</span></p> </td>
<td class="prngen5"> <p class="prnews_p"><span class="prnews_span">INT8</span></p> </td>
<td class="prngen5"> <p class="prnews_p"><span class="prnews_span">56.79%</span></p> </td>
<td class="prngen5"> <p class="prnews_p"><span class="prnews_span">79.76%</span></p> </td>
<td class="prngen6"> <p class="prnews_p"><span class="prnews_span">1456</span></p> </td>
</tr>
</tbody>
</table>
</div>
<p>TF2 w/ F10A VS GPU</p>
<p>The Inspur TF2 computing acceleration engine improves the AI calculation performance on the FPGA through the technical innovations such as shift calculation and model optimization, and lowers the AI software implementation threshold of the FPGA. It supports the FPGA to be widely used in the AI ecosystem to promote more AI applications. Inspur plans to open TF2 to its AI customers, and will continue to upgrade and develop optimization technologies that can support multiple models, the latest deep neural network model and FPGA accelerator cards using with the latest chip. It is expected that the performance of the next-generation high-performance FPGA accelerator card will be three times of F10A.</p>
<p>Inspur is the world's leading AI computing platform provider, offering a four-layer AI stack of computing hardware, management suite, framework optimization, and application acceleration to build an agile, efficient, and optimized AI infrastructure. Inspur has become the most important AI server supplier for Baidu, Ali and <span class="xn-money">Tencent</span>, and has maintained close collaboration in systems and applications with leading AI companies such as Iflytek, SenseTime, Fac++, Toutiao and Didi. Inspur strives to help AI customers achieve maximum application performance improvement in voice, image, video, search engine, and network. According to IDC's 2017 China AI Infrastructure Market Research Report, Inspur's AI server market share reached 57% in the last year.</p>
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style="-moz-hyphens:none;-webkit-hyphens:none;Margin:0;Margin-bottom:10px;color:#fff;font-family:Montserrat,Arial,sans-serif;font-size:18px;font-weight:400;hyphens:none;line-height:22px;margin:0;margin-bottom:10px;padding:0;text-align:center;text-transform:uppercase;word-break:none;word-wrap:normal">News From Inspur Electronic Information Industry Co., Ltd</h4><h5 class="text-center" style="-moz-hyphens:none;-webkit-hyphens:none;Margin:0;Margin-bottom:10px;color:#fff;font-family:Montserrat,Arial,sans-serif;font-size:14px;font-weight:500;hyphens:none;line-height:18px;margin:0;margin-bottom:0;padding:0;text-align:center;word-break:none;word-wrap:normal">Transmitted by PR Newswire for Journalists on <span class="prevent-break" style="display:inline-block">August 24, 2018 06:20 PM EST </span></h5></th><th class="expander" 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style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0;text-align:left"> <table class="spacer" style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><td height="24px" style="-moz-hyphens:auto;-webkit-hyphens:auto;Margin:0;border-collapse:collapse!important;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:24px;font-weight:400;hyphens:auto;line-height:24px;margin:0;mso-line-height-rule:exactly;padding:0;text-align:left;vertical-align:top;word-wrap:break-word"> </td></tr></tbody></table> <h1 style="Margin:0;Margin-bottom:10px;color:#4D4E53;font-family:Montserrat,Arial,sans-serif;font-size:20px;font-weight:500;line-height:28px;margin:0;margin-bottom:0;padding:0;text-align:left;word-wrap:normal">Inspur Releases TensorFlow-Supported FPGA Compute Acceleration Engine TF2</h1> <table class="spacer" style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><td height="24px" style="-moz-hyphens:auto;-webkit-hyphens:auto;Margin:0;border-collapse:collapse!important;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:24px;font-weight:400;hyphens:auto;line-height:24px;margin:0;mso-line-height-rule:exactly;padding:0;text-align:left;vertical-align:top;word-wrap:break-word"> </td></tr></tbody></table> </th><th class="expander" style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0!important;text-align:left;visibility:hidden;width:0"></th></tr></table></th> </tr></tbody></table> <table class="row content" style="background:#fff;border-collapse:collapse;border-spacing:0;display:table;padding:0;position:relative;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><th class="small-12 large-12 columns first last" style="Margin:0 auto;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0 auto;padding:0;padding-bottom:16px;padding-left:30px;padding-right:30px;text-align:left;width:570px"><table style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tr style="padding:0;text-align:left;vertical-align:top"><th style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0;text-align:left"> <table class="spacer" style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><td height="24px" style="-moz-hyphens:auto;-webkit-hyphens:auto;Margin:0;border-collapse:collapse!important;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:24px;font-weight:400;hyphens:auto;line-height:24px;margin:0;mso-line-height-rule:exactly;padding:0;text-align:left;vertical-align:top;word-wrap:break-word"> </td></tr></tbody></table><p><span class="xn-location">FREMONT, Calif.</span>, <span class="xn-chron">Aug. 24, 2018</span> /PRNewswire/ -- On <span class="xn-chron">August 23</span>, at KDD2018 <span class="xn-location">London</span> -- a premier global conference focused on artificial intelligence -- Inspur released the FPGA computing acceleration engine TF2 supporting TensorFlow, which helps AI customers quickly implement FPGAs based on mainstream AI training software and deep neural network model DNN on inference. It delivers high performance and low latency for AI applications through the world's first DNN shifting technology on FPGAs.</p>
<p>At present, using the FPGA technology to achieve customizable, low latency, high performance and high power-consumption ratio for AI inference application has become the technical route adopted by many AI companies. However, before FPGA technology enters into large-scale AI business deployment, there are still many challenges such as high software writing threshold, limited performance optimization, and difficult power control. The goal of Inspur's TF2 Compute Acceleration Engine is to solve these challenges for customers. </p>
<p>The TF2 computing acceleration engine consists of two parts. The first part is the model optimization conversion tool TF2 Transform Kit, which optimizes and transforms the deep neural network model data trained by the framework such as TensorFlow. It greatly reduces the size of the model data file, as it can compress 32-bit floating-point model data into a 4-bit integer data model, making the actual model data file size smaller than the original 1/8 and basically keeps the rule storage of the original model data. The second part is the FPGA intelligent running engine TF2 Runtime Engine. It can automatically convert the previously optimized model file into FPGA target running file. In order to eliminate the dependence of deep neural network such as CNN on FPGA floating-point computing power, Inspur designed the innovative shift computing technology, which can quantize 32-bit float-point into 8-bit integer data. Combined with the aforementioned 4-bit integer model data, the conversion convolution operation floating-point multiplication is calculated as an 8-bit integer shift operation, which greatly improves the FPGA for inference calculation performance and effectively reduces its actual operating power consumption. This is also the world's first case of implementing the shift operation of deep neural network DNN on FPGA under the premise of maintaining the accuracy of the original model.</p>
<p>The SqueezeNet model on the Inspur F10A FPGA card shows excellent computational performance for the TF2 computing acceleration engine. The F10A is the world's first half-height and half-length FPGA accelerator card to support the Arria 10 chip. SqueezeNet is a typical convolutional neural network architecture which is a streamlining model but its accuracy is comparable to AlexNet. It is especially suitable for image-based AI applications with high real-time requirements. Running the SqueezeNet model optimized by the TF2 engine on the F10A, the calculation time of a single picture is 0.674ms while maintaining the original accuracy. It is slightly better than the currently widely used GPU P4 accelerator card in terms of calculation accuracy and delay. </p>
<div>
<table border="1" cellpadding="0" cellspacing="0" class="prntblns">
<tbody>
<tr>
<td class="prnsbts prnrbrs prnvab prnsbbs prntac prnpl6 prnsbls prnpr6"> <p class="prnews_p"><span class="prnews_span">Device</span></p> </td>
<td class="prngen3"> <p class="prnews_p"><span class="prnews_span">Peak Power</span></p> </td>
<td class="prngen3"> <p class="prnews_p"><span class="prnews_span">Date Type</span></p> </td>
<td class="prngen3"> <p class="prnews_p"><span class="prnews_span">Top1</span></p> </td>
<td class="prngen3"> <p class="prnews_p"><span class="prnews_span">Top5</span></p> </td>
<td class="prngen3"> <p class="prnews_p"><span class="prnews_span">FPS (images/s)</span></p> </td>
</tr>
<tr>
<td class="prngen4"> <p class="prnews_p"><span class="prnews_span">F10A </span></p> </td>
<td class="prngen5"> <p class="prnews_p"><span class="prnews_span">45W</span></p> </td>
<td class="prngen5"> <p class="prnews_p"><span class="prnews_span">INT8</span></p> </td>
<td class="prngen5"> <p class="prnews_p"><span class="prnews_span">57.62%</span></p> </td>
<td class="prngen5"> <p class="prnews_p"><span class="prnews_span">79.98%</span></p> </td>
<td class="prngen6"> <p class="prnews_p"><span class="prnews_span">1484</span></p> </td>
</tr>
<tr>
<td class="prngen4"> <p class="prnews_p"><span class="prnews_span">P4</span></p> </td>
<td class="prngen5"> <p class="prnews_p"><span class="prnews_span">75W</span></p> </td>
<td class="prngen5"> <p class="prnews_p"><span class="prnews_span">FP32</span></p> </td>
<td class="prngen5"> <p class="prnews_p"><span class="prnews_span">58.14%</span></p> </td>
<td class="prngen5"> <p class="prnews_p"><span class="prnews_span">80.79%</span></p> </td>
<td class="prngen6"> <p class="prnews_p"><span class="prnews_span">1323</span></p> </td>
</tr>
<tr>
<td class="prngen4"> <p class="prnews_p"><span class="prnews_span">P4</span></p> </td>
<td class="prngen5"> <p class="prnews_p"><span class="prnews_span">75W</span></p> </td>
<td class="prngen5"> <p class="prnews_p"><span class="prnews_span">INT8</span></p> </td>
<td class="prngen5"> <p class="prnews_p"><span class="prnews_span">56.79%</span></p> </td>
<td class="prngen5"> <p class="prnews_p"><span class="prnews_span">79.76%</span></p> </td>
<td class="prngen6"> <p class="prnews_p"><span class="prnews_span">1456</span></p> </td>
</tr>
</tbody>
</table>
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<p>TF2 w/ F10A VS GPU</p>
<p>The Inspur TF2 computing acceleration engine improves the AI calculation performance on the FPGA through the technical innovations such as shift calculation and model optimization, and lowers the AI software implementation threshold of the FPGA. It supports the FPGA to be widely used in the AI ecosystem to promote more AI applications. Inspur plans to open TF2 to its AI customers, and will continue to upgrade and develop optimization technologies that can support multiple models, the latest deep neural network model and FPGA accelerator cards using with the latest chip. It is expected that the performance of the next-generation high-performance FPGA accelerator card will be three times of F10A.</p>
<p>Inspur is the world's leading AI computing platform provider, offering a four-layer AI stack of computing hardware, management suite, framework optimization, and application acceleration to build an agile, efficient, and optimized AI infrastructure. Inspur has become the most important AI server supplier for Baidu, Ali and <span class="xn-money">Tencent</span>, and has maintained close collaboration in systems and applications with leading AI companies such as Iflytek, SenseTime, Fac++, Toutiao and Didi. Inspur strives to help AI customers achieve maximum application performance improvement in voice, image, video, search engine, and network. According to IDC's 2017 China AI Infrastructure Market Research Report, Inspur's AI server market share reached 57% in the last year.</p>
<p>SOURCE Inspur Electronic Information Industry Co., Ltd</p>CONTACT: Juno Shi, +1-408-714-9068, shillbj@inspur.com<table class="spacer" style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><td height="8px" style="-moz-hyphens:auto;-webkit-hyphens:auto;Margin:0;border-collapse:collapse!important;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:8px;font-weight:400;hyphens:auto;line-height:8px;margin:0;mso-line-height-rule:exactly;padding:0;text-align:left;vertical-align:top;word-wrap:break-word"> </td></tr></tbody></table> <table class="button medium expand" style="Margin:0 0 16px 0;border-collapse:collapse;border-spacing:0;margin:0 0 16px 0;padding:0;text-align:left;vertical-align:top;width:100%!important"><tr style="padding:0;text-align:left;vertical-align:top"><td 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